verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit9”---Sequential circuit9

1、题目2、分析当a0时q每个时钟周期加1当a1时q保持为4不变q从0变化到63、代码module top_module ( input clk, input a, output reg [3:0] q ); always (posedge clk) begin if (a 1b1)begin q 4d4; end else if (q 4d6)begin q 4d0; end else q q 4d1; end endmodule4、结果