[Synth 8-6090] variable n_state_fifo_poll is written by both blocking and non-blocking assignments, entire logic could be removed [D:/xianyv/007_18_1/ad7606_parallel2usb/ad7606_parallel2usb.srcs/sources_1/new/USB30_streamIN.v:104]核心问题同一个变量n_state_fifo_poll一行用了阻塞赋值另一行用了非阻塞赋值Verilog 语法严格禁止FPGA 综合工具无法识别这种矛盾逻辑直接删除这段电路 → 你的状态机直接失效